Counterfeits are a growing concern in the electronics industry. Robert Lowry, a principal of AJA, is a noted expert in the field. He is available to assist you in identifying counterfeit issues and related problems. Mr. Lowry has also given short courses on the topic. These courses are available from AJA and can be given to your staff, onsite or off.

For more see Mr. Lowry’s posts on The Reliability Times.

AJA is proud to announce our participation in the Medical Device Materials Task Force (MDMT). The MDMT's mission is to foster extended discussions on technical and materials issues specific to the Medical Device Community. Our goal is to cultivate a cooperative spirit in an open discussion of current materials issues facing Medical Device manufacturers in a collegial and secure environment.

In the 1970s, moisture-induced corrosion plagued reliability of sealed microelectronic devices in critical military, space, and defense systems. The problem was a foremost topic at prominent reliability and technical symposia at the time, including focus meetings at NBS (now NIST) in 1978 and 1984. But the matter was not really being addressed at the grassroots technical level. In 1984, under the leadership of Dr. Bob Thomas, then of Rome Air Development Center, a small group of invited scientists first gathered to discuss issues of moisture in microelectronics at the Minnowbrook NY Conference Center of Syracuse University.

The meeting was unique in that it was informal with no set program or agenda. It encouraged communication among otherwise competitive or adversarial entities to seek solutions for the larger good of solving a basic problem, in a manner which would not threaten but rather enhance both companies’ competitiveness and users’ confidence in their products. There were no management or regulatory attendees at these meetings. No minutes, proceedings, or other records were published. Scientists took 3 meals per day together in the conference center dining room. They met in informal morning and evening conference room sessions. They took advantage of the center’s remote sylvan surroundings by hiking, sailing, golfing, sightseeing, and other recreational opportunities during the afternoons. They re-convened at the bar after evening sessions, discussions often continuing into the wee hours.

Significant understandings, working relationships, and friendships developed between materials suppliers, device manufacturers, and component users as Minnowbrook Conferences continued each year. As many (if not more) understandings developed on the lake, hiking up Blue Mountain, or at the bar, as in the conference room. Significant progress began to occur in efforts to measure and control moisture in microelectronics, leading to successful approaches to the problem over the next several years. Moisture is a sinister foe, and the Minnowbrook Conference continues on the topic even today, along with broader topics of interest to the electronics community.

Four years ago, Dr. Thomas, one of AJA's founders, noted the need in the medical device community for a communicative forum similar to that of the Minnowbrook Moisture Conferences. It is the spirit of collegiality and cooperative problem solving of Minnowbrook, applied to medical device materials issues under the unifying goal of saving human life, mitigating pain, and reducing the cost of medical care, that Arthur Jonath Associates seeks to cultivate via the Medical Device Materials Task Force.

For more information on the MDMT click here...

WAFER-LEVEL THREE-DIMENSIONAL (3D) INTEGRATION:

FUTURE OPPORTUNITIES AND PROCESSING NEEDS

A one day seminar by Dr. Ron Gutmann, AJA’s Sr. Associate specializing in advanced electronic materials, processing techniques, semiconductor devices, characterization techniques and IC design.

Packaging of integrated circuit chips has evolved from 2D planar assemblies to 3D chip stacks, with peripheral wire bonding to a substrate. This technology’s principal driver is space conservation, especially for a myriad of wireless products. Using thinned die, designers may package 3-5 dies into the space of a single, full-thickness die. In order to enhance the performance of the inter-die interconnects (in particular, reduce the inductance), through-silicon or through-strata via (TSV) technology is currently being introduced for high-speed, high-frequency applications. Challenges include die-to-die alignment and bonding, TSV processing, and design tools (particularly for processor-based systems). The technology will be in wide-scale manufacturing within a few years.

While this packaging technology provides the high-performance inter-die interconnects (due to the elimination of wire-bond inductance), the assembly cost involved in die-to-die alignment can be significant, particularly with small die. Die-to-wafer assembly costs will be lower, but the number of strata will be limited. The holy grail of 3D integration is to establish a manufacturing technology with multiple active silicon layers stacked using interconnect structures that align and interconnect the active layers for system-on-a-chip (SoC) high-performance applications. Such a technology is “wafer-level 3D integration”.

Wafer-level 3D integration includes wafer-level alignment and bonding, wafer-level thinning, wafer-scale TSV technology and, possibly, wafer-level packaging (WLP). In the last 10-15 years, research and development activities at various universities, industrial consortia, large companies and start-ups have established different approaches for such a wafer-level 3D integration technology. While no company has yet announced a commitment to a specific manufacturing technology, the design community needs to become aware of the opportunities that will be coming shortly.

AJA is ready to provide a one-day seminar on the various wafer-level 3D integration technologies, including the advantages and disadvantages of each, who is doing what, representative applications and, on a one-on-one basis, what’s relevant for your company.